During a press event here, an Intel engineer ran a SunGard financial modeling application on a preproduction server based on the Tigerton processor. In total, the server used four Tigertons, each with four cores, for a total of 16 independent processing cores.
Intel hopes to launch Tigerton as part of its Xeon MP chip family in the third quarter of 2007. At the event, the chipmaker also outlined its plans for ramping up its production of quad-core chips.
Tigerton will be the first processor for the MP lineup to use Intel's Core microarchitecture, which is more powerful and power-efficient than the Netburst microarchitecture it replaced. Intel has already made the transition to Core in its desktop, notebook and dual-processor server products, but is still selling chips for multiprocessor servers based on Netburst.
In addition, servers based on Tigerton will use the Clarksboro chipset. Clarksboro eliminates the dual-independent bus structure used on current Tulsa-class servers and replaces it with a dedicated link between each quad-core chip and the chipset.
Intel's current design for four-processor servers calls for two processors to share a single connection to the chipset. This leads to a bottleneck, or competition for access to that narrow connection.
Clarksboro will also introduce fully buffered memory to the MP lineup.
Intel believes it will have shipped more than 1 million quad-core processors by the middle of 2007, said Stephen Smith, the director of business operations for Intel's Digital Enterprise Group. This total includes the Kentsfield quad-core processor for high-end desktops and the Clovertown processor for dual-processor servers. Both of those chips are expected to become available in systems during November.
